John Backes

About John

My research interests include logic synthesis, formal verification, technology mapping, and SAT-based algorithms.

John's Papers

Journal Papers

title: The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability authors: John Backes, Brian Fett and Marc Riedel submitted to: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010.

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title: The Synthesis of Stochastic Circuits for Nanoscale Computation authors: Weikang Qian, John Backes, and Marc Riedel presented at: International Journal of Nanotechnology and Molecular Computation, 2010.

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Slides

Conference Papers

title: Resolution Proofs as a Data Structure For Logic Synthesis authors: John Backes and Marc Riedel to be presented at: The International Workshop On Logic Syntehsis, San Diego, CA, 2011.

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title: Reduction of Interpolants For Logic Synthesis authors: John Backes and Marc Riedel presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2010. presented at: International Workshop on Logic and Synthesis, Irvine, CA, 2010.

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Slides

title: The Synthesis of Cyclic Dependencies with Craig Interpolation authors: John Backes and Marc Riedel presented at: International Workshop on Logic and Synthesis, Berkeley, CA, 2009.

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Slides

title: The Analysis of Cyclic Circuits with Boolean Satisfiability authors: John Backes, Brian Fett and Marc Riedel presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2008.

Paper

Slides

Contact Information

• Email:
• Phone: (952) 239-7828