John Backes

About John

My research interests include Logic Synthesis, Formal Verification, Technology Mapping, and SAT-Based Algorithms. I formally started the PhD program at UMN in May 2009; however, I've been an informal PhD student for quite some time.

John's Papers

title: The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability authors: John Backes, Brian Fett and Marc Riedel submitted to: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Paper

title: Reduction of Interpolants For Logic Synthesis authors: John Backes and Marc Riedel presented at: International Workshop on Logic and Synthesis, Irvine, CA, 2010. to be presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2010.

Paper

Slides

title: The Synthesis of Cyclic Dependencies with Craig Interpolation authors: John Backes and Marc Riedel presented at: International Workshop on Logic and Synthesis, Berkeley, CA, 2009.

Paper

Slides

title: The Analysis of Cyclic Circuits with Boolean Satisfiability authors: John Backes, Brian Fett and Marc Riedel presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2008.

Paper

Slides

title: The Synthesis of Stochastic Circuits for Nanoscale Computation authors: Weikang Qian, John Backes, and Marc Riedel presented at: International Workshop on Logic and Synthesis, San Diego, CA, 2007.

Paper

Slides

Contact Information

• Email:
• Phone: (952) 239-7828