Difference between revisions of "John Backes"

Revision as of 15:29, 3 May 2011

My research interests include logic synthesis, formal verification, technology mapping, and SAT-based algorithms.

Journal Papers

title:	The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability
authors:	John Backes, Brian Fett and Marc Riedel
submitted to:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010.

title:	The Synthesis of Stochastic Circuits for Nanoscale Computation
authors:	Weikang Qian, John Backes, and Marc Riedel
presented at:	International Journal of Nanotechnology and Molecular Computation, 2010.

Conference Papers

title:	Resolution Proofs as a Data Structure For Logic Synthesis
authors:	John Backes and Marc Riedel
to be presented at:	The International Workshop On Logic Syntehsis, San Diego, CA, 2011.

title:	Reduction of Interpolants For Logic Synthesis
authors:	John Backes and Marc Riedel
presented at:	The International Conference on Computer-Aided Design, San Jose, CA, 2010.
presented at:	International Workshop on Logic and Synthesis, Irvine, CA, 2010.

title:	The Synthesis of Cyclic Dependencies with Craig Interpolation
authors:	John Backes and Marc Riedel
presented at:	International Workshop on Logic and Synthesis, Berkeley, CA, 2009.

title:	The Analysis of Cyclic Circuits with Boolean Satisfiability
authors:	John Backes, Brian Fett and Marc Riedel
presented at:	The International Conference on Computer-Aided Design, San Jose, CA, 2008.

@@ Line 70: / Line 70: @@
 |- valign=top
 |  width="100" | '''title''':
-|  width="510" | [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf‎‎‎ | Resolution Proofs as a Data Structure For Logic Synthesis]]
+|  width="507" | [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf‎‎‎ | Resolution Proofs as a Data Structure For Logic Synthesis]]
 |-
 | '''authors''':