Difference between revisions of "John Backes"
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[[Media:BackesIWLS08.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]] | [[Media:BackesIWLS08.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]] | ||
[[Media:The_Synthesis_of_Stochastic_Logic_for_Nanoscale_Computation.pdf | The Synthesis of Stochastic Logic for Nanoscale Computation]] | [[Media:The_Synthesis_of_Stochastic_Logic_for_Nanoscale_Computation.pdf | The Synthesis of Stochastic Logic for Nanoscale Computation]] | ||
Revision as of 12:39, 20 June 2008
About John:
My research interests include Logic Synthesis, Verification, and Technology Mapping. I will graduate with my undergraduate degree in Computer Engineering in May of 2009.
Papers that John has contributed too:
