Difference between revisions of "John Backes"

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'''Papers that John has contributed too:'''
 
'''Papers that John has contributed too:'''
[[Media:IWLS08_Backes_Fett_Riedel_The_Analysis_of_Cyclic_Circuits_with_Boolean_Satisfiability.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]]
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[[Media:BackesIWLS08.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]]

Revision as of 11:36, 20 June 2008

About John:

My research interests include Logic Synthesis, Verification, and Technology Mapping. I will graduate with my undergraduate degree in Computer Engineering in May of 2009.

Papers that John has contributed too: The Analysis of Cyclic Circuits with Boolean Satisfiability