Difference between revisions of "John Backes"

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<br>[[Media:Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf  | Paper]]
 
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Revision as of 10:48, 22 December 2010

John Backes.jpg

About John

My research interests include Logic Synthesis, Formal Verification, Technology Mapping, and SAT-Based Algorithms. I formally started the PhD program at UMN in May 2009; however, I've been an informal PhD student for quite some time.

John's Papers

title: The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability
authors: John Backes, Brian Fett and Marc Riedel
submitted to: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
       

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Paper

title: Reduction of Interpolants For Logic Synthesis
authors: John Backes and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2010.
       

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Paper

       

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Slides

title: The Synthesis of Cyclic Dependencies with Craig Interpolation
authors: John Backes and Marc Riedel
presented at: International Workshop on Logic and Synthesis, Berkeley, CA, 2009.
       

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Paper

       

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Slides

title: The Analysis of Cyclic Circuits with Boolean Satisfiability
authors: John Backes, Brian Fett and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2008.
       

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Paper

       

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Slides

title: The Synthesis of Stochastic Circuits for Nanoscale Computation
authors: Weikang Qian, John Backes, and Marc Riedel
presented at: International Workshop on Logic and Synthesis, San Diego, CA, 2007.
       

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Paper

       

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Slides

Contact Information

  • Email: BackesEmail.gif
  • Phone: (952) 239-7828