Difference between revisions of "John Backes"

From The Circuits and Biology Lab at UMN
Jump to navigationJump to search
 
(91 intermediate revisions by 3 users not shown)
Line 3: Line 3:
==About John==
==About John==


My research interests include Logic Synthesis, Verification, Technology Mapping, and SAT-Based Algorithms. I will earn my bachelor's degree in Computer Engineering in May of 2009.
I completed my Ph.D. under [[Marc Riedel | Prof. Marc Riedel]] in 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at [http://www.rockwellcollins.com/ Rockwell Collins]


==Papers that John has contributed too==
== John's Papers ==


[[Media:BackesIWLS08.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]]
'''Dissertation'''


[[Media:The_Synthesis_of_Stochastic_Logic_for_Nanoscale_Computation.pdf | The Synthesis of Stochastic Logic for Nanoscale Computation]]
{|
| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
|  width="100" | '''title''':
|  width="500" | [[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf |Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability]]
|-
| '''author''':
| [[John Backes]]
|-
| '''Dissertation''':
| Ph.D., [http://www.ece.umn.edu Electrical and Computer Engineering], [http://www.umn.edu University of Minnesota], 2013.
|}
| align=center width="70" |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/9/96/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pdf | Paper]]
| align=center width="70" |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
<br> [http://www.mriedel.ece.umn.edu/wiki/images/f/fa/Backes_Algorithms_And_Data_Structures_For_Logic_Synthesis_And_Verification_Using_Boolean_Satisfiability.pptx Slides]
|}
 
'''Journal Papers'''
 
{|
| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
|  width="100" | '''title''':
|  width="500" | [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf‎ | The Synthesis of Cyclic Dependencies with Boolean Satisfiability]]
|-
| '''authors''':
| [[John Backes]]  and [[Marc Riedel]]
|-
| '''appeared&nbsp;in''':
| [http://todaes.acm.org/ ACM Transactions on Design Automation of Electronic Systems], 2012.
|}
| align=center |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/d/df/Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Boolean_Satisfiability.pdf‎  | Paper]]
|}
<!--
{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf | The Analysis and Mapping of Cyclic Circuits with Boolean Satisfiability]]
|- valign="top"
| '''authors''':
| [[John Backes]], [[Brian Fett]], and [[Marc Riedel]]
|- valign="top"
| '''submitted&nbsp;to''':
| [http://jsat.ewi.tudelft.nl/ Journal on Satisfiability, Boolean Modeling and Computation], 2011.
|}
| align=center |
<span class="plainlinks">
[http://www.mriedel.ece.umn.edu/wiki/images/6/66/Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Fett_Riedel_The_Analysis_And_Mapping_Of_Cyclic_Cricuits_With_Boolean_Satisfiability.pdf  | Paper]]
|}
-->
{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf | The Synthesis of Stochastic Circuits for Nanoscale Computation]]
|- valign="top"
| '''authors''':
| [[Weikang Qian]], [[John Backes]], and [[Marc Riedel]]
|- valign="top"
| '''appeared&nbsp;in''':
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description International Journal of Nanotechnology and Molecular Computation], <br>vol. 1, no. 4, pp. 39&ndash;57, 2010.
|}
| align=center width="70 |
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/a/a8/Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Qian_Backes_Riedel_The_Synthesis_of_Stochastic_Circuits_for_Nanoscale_Computation_IJNMC.pdf | Paper]]
|}
 
'''Conference Papers'''
 
{|
 
| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
|  width="100" | '''title''':
|  width="500" | [[Media:Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf‎ ‎‎‎ | Using Cubes of Non-state Variables With Property Directed Reachability]]
|-
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|-
| '''presented&nbsp;at''':
| [http://www.date-conference.com/ Design Automation & Test in Europe], Grenoble, France, 2013.
|}
| align=center width="70" |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/c/c0/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pdf‎  | Paper]]
| align=center width="70" |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/4/41/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pptx http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
<br> [http://www.mriedel.ece.umn.edu/wiki/images/4/41/Backes_Riedel_Using_Cubes_of_Non-State_Variables_With_Property_Directed_Reachability.pptx Poster]
 
|}
 
{|
 
| rowspan=2 |
{| style="background:#F0E68C"
|- valign=top
|  width="100" | '''title''':
|  width="500" | [[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf‎‎‎ | Resolution Proofs as a Data Structure For Logic Synthesis]]
|-
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|-
| '''presented&nbsp;at''':
| [http://iwls.org/ The International Workshop on Logic Synthesis], La Jolla, CA, 2011.
|}
| align=center width="70" |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/2/27/Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Riedel_Resolution_Proofs_As_A_Data_Structure_For_Logic_Synthesis.pdf  | Paper]]
| align=center width="70" |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/5/5e/Iwls2011final_final.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
<br> [http://cctbio.ece.umn.edu/wiki/images/f/f1/Backes_Riedel_Resolution_Proofs_as_a_Data_Structure_for_Logic_Synthesis.ppt Slides]
 
|}
 
{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf‎‎ | Reduction of Interpolants For Logic Synthesis]]
|- valign="top"
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|- valign="top"
| '''presented&nbsp;at''':
| [http://www.iccad.com The International Conference on Computer-Aided Design], San Jose, CA, 2010.
|}
| align=center width="70" |
<span class="plainlinks">[http://cadbio.com/wiki/images/b/b6/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.pdf  | Paper]]
| align=center width="70" |
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/0/00/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
<br> [http://cctbio.ece.umn.edu/wiki/images/0/00/Backes_Riedel_Reduction_Of_Interpolants_For_Logic_Synthesis.ppt Slides]
|}
{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf‎ | The Synthesis of Cyclic Dependencies with Craig Interpolation]]
|- valign="top"
| '''authors''':
| [[John Backes]] and [[Marc Riedel]]
|- valign="top"
| '''presented&nbsp;at''':
| [http://www.sigda.org/iwls/iwls2009 The International Workshop on Logic and Synthesis], Berkeley, CA, 2009.
|}
| align=center width="70" |
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/e/ec/Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Riedel_The_Synthesis_of_Cyclic_Dependencies_with_Craig_Interpolation.pdf‎  | Paper]]
| align=center width="70" |
<span class="plainlinks">[http://www.mriedel.ece.umn.edu/wiki/images/a/ad/Backes_Riedel_The_Synthesis_Of_Functional_Dependencies_With_Craig_Interpolation.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
<br> [http://www.mriedel.ece.umn.edu/wiki/images/a/ad/Backes_Riedel_The_Synthesis_Of_Functional_Dependencies_With_Craig_Interpolation.ppt Slides]
|}
{|
|
{| style="background:#F0E68C"
|- valign="top"
| width="100" | '''title''':
| width="500" | [[Media:Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf | The Analysis of Cyclic Circuits with Boolean Satisfiability]]
|- valign="top"
| '''authors''':
| [[John Backes]], [[Brian Fett]], and [[Marc Riedel]]
|- valign="top"
| '''presented&nbsp;at''':
| [http://www.iccad.com/events/eventdetails.aspx?id=86-2-B The International Conference on Computer-Aided Design], San Jose, CA, 2008.
|}
| align=center width="70" |
<span class="plainlinks">[http://cctbio.ece.umn.edu/wiki/images/8/84/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf http://cctbio.ece.umn.edu/wiki/images/0/04/Pdf.jpg]</span>
<br>[[Media:Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.pdf  | Paper]]
| align=center width="70" |
<span class="plainlinks">[http://cctbio.ece.umn.edu/files/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.ppt http://cctbio.ece.umn.edu/wiki/images/3/36/Ppt.jpg]</span>
<br> [http://cctbio.ece.umn.edu/files/Backes_Riedel_The_Analysis_of_Cyclic_Circuits_With_Boolean_Satisfiability.ppt Slides]
|}


== Contact Information ==
== Contact Information ==

Latest revision as of 17:28, 24 November 2015

John Backes.jpg

About John

I completed my Ph.D. under Prof. Marc Riedel in 2013. My research pertained to logic synthesis, technology mapping, SAT-based algorithms, and model checking. I am now a Senior Research Scientist at Rockwell Collins

John's Papers

Dissertation

title: Algorithms and Data Structures For Logic Synthesis And Verification Using Boolean Satisfiability
author: John Backes
Dissertation: Ph.D., Electrical and Computer Engineering, University of Minnesota, 2013.

Pdf.jpg
Paper

Ppt.jpg
Slides

Journal Papers

title: The Synthesis of Cyclic Dependencies with Boolean Satisfiability
authors: John Backes and Marc Riedel
appeared in: ACM Transactions on Design Automation of Electronic Systems, 2012.

Pdf.jpg
Paper

title: The Synthesis of Stochastic Circuits for Nanoscale Computation
authors: Weikang Qian, John Backes, and Marc Riedel
appeared in: International Journal of Nanotechnology and Molecular Computation,
vol. 1, no. 4, pp. 39–57, 2010.

Pdf.jpg
Paper

Conference Papers

title: Using Cubes of Non-state Variables With Property Directed Reachability
authors: John Backes and Marc Riedel
presented at: Design Automation & Test in Europe, Grenoble, France, 2013.

Pdf.jpg
Paper

Ppt.jpg
Poster

title: Resolution Proofs as a Data Structure For Logic Synthesis
authors: John Backes and Marc Riedel
presented at: The International Workshop on Logic Synthesis, La Jolla, CA, 2011.

Pdf.jpg
Paper

Ppt.jpg
Slides

title: Reduction of Interpolants For Logic Synthesis
authors: John Backes and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2010.

Pdf.jpg
Paper

Ppt.jpg
Slides

title: The Synthesis of Cyclic Dependencies with Craig Interpolation
authors: John Backes and Marc Riedel
presented at: The International Workshop on Logic and Synthesis, Berkeley, CA, 2009.

Pdf.jpg
Paper

Ppt.jpg
Slides

title: The Analysis of Cyclic Circuits with Boolean Satisfiability
authors: John Backes, Brian Fett, and Marc Riedel
presented at: The International Conference on Computer-Aided Design, San Jose, CA, 2008.

Pdf.jpg
Paper

Ppt.jpg
Slides

Contact Information

  • Email: BackesEmail.gif
  • Phone: (952) 239-7828
Retrieved from "http://mriedel.ece.umn.edu/wiki/index.php?title=John_Backes&oldid=100942"